(1) Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more particularly to a semiconductor device having a stacked capacitor type memory cell.
(2) Description of the Related Art
A conventional stacked capacitor type memory cell is shown in sectional view in FIG. 1. As seen therein, there are provided a p-type silicon substrate 901; a field oxide film 902 formed on the silicon substrate 901 by a LOCOS (local oxidation of silicon) method for element isolation; a gate oxide film 903; a gate electrode 904 which functions also as a word line; a first n-type diffusion layer 905 and a second n-type diffusion layer 906 which respectively constitute a first source/drain region and a second source/drain region; a silicon oxide film 907 which covers a transistor; a first contact hole 910 formed in the silicon oxide film 907 for establishing contact with the first n-type diffusion layer 905; a first electrode 912 of a capacitor which is in contact with the first n-type diffusion layer 905 through the first contact hole 910; a dielectric film 913; a second electrode 914 of the capacitor which surrounds the first electrode 912 through the dielectric film 913; an interlayer insulating film 915 of BPSG (Boro-phospho-silicate glass); a second contact hole 916 formed in the interlayer insulating film 915 and the silicon oxide film 907 for establishing contact with the second n-type diffusion layer 906; and a bit line 917 of Al (aluminum) which is in contact with the second n-type diffusion layer 906 through the second contact hole 916.
FIGS. 2A-2D show, in sectional views, sequential fabrication steps of the method for fabricating the conventional stacked capacitor type memory cell described above.
First, FIG. 2A is referred to. After the field oxide film 902 is formed by selectively oxidizing a surface of the p-type silicon substrate 901, a surface of the active region that is not covered by the field oxide film 902 is oxidized to form the gate oxide film 903. Polycrystalline silicon containing impurities is caused to grow on the entire surface and, then, the resulting film is patterned to form the gate electrode 904. Thereafter, arsenic (As) is ion-implanted in the entire surface to form the n-type diffusion layers 905 and 906 which serve as source/drain regions.
Next, as seen in FIG. 2B, the silicon oxide film 907 and the silicon nitride film 908 as a pad material are caused to grow on the entire surface by using a chemical vapor deposition (CVD) process and, then, the first contact hole 910 is formed on the first n-type diffusion layer 905 by opening the silicon oxide film 907 and the silicon nitride film 908. Then, the impurity doped polycrystalline silicon film 912a is formed on the entire surface.
Referring to FIG. 2C, the resulting films are subjected to the patterning in such a way as to leave the polycrystalline silicon film 912a, which contains the first contact hole 910, and the silicon nitride film 908, whereby the first electrode 912 of the capacitor is formed. Thereafter, as shown in FIG. 2D, the silicon nitride film 908 under the first electrode 912 is removed by wet-etching. Then, by performing thermal oxidation, the dielectric film 913 is formed on the surface of the first electrode 912.
Next, the doped polycrystalline silicon film is caused to grow on the entire surface so as to have the first electrode 912 surrounded thereby, and this film is patterned into a shape that leaves in place the portion of the film that faces the first electrode 912, whereby the second electrode 914 of the capacitor is formed. This is followed by the growth of the interlayer insulating film 915 on the entire surface, and the second contact hole 916 is formed in this film and the silicon oxide film 907 to establish contact with the second n-type diffusion layer 906. Finally, an Al (aluminum) film is deposited by a spattering method and is patterned to form a bit line 917, which completes the fabrication of the semiconductor device as shown in FIG. 1.
In the conventional semiconductor device explained above, the first electrode 912 of the capacitor is in direct contact with the first n-type diffusion layer 905 so that, from the time when the silicon nitride film 908 is removed to the time when the polycrystalline silicon film is deposited for forming the second electrode 914, the weight of the outwardly extended portion of the first electrode 912 must be supported by the vertical portion of the first electrode 912 and, thus, this vertical portion is under a heavy stress. This tends to cause cracks to occur in the vertical portion resulting in the development of breakage therein due even to a small external force during the fabrication of the device with the production yield greatly lowered. Where such breakage has developed in the first electrode 912, the broken part may adhere as a foreign matter to other parts or devices on the wafer, resulting in secondary causes for the occurrence of defects in the product.